Our British Patent No. 2311882, the contents of which are incorporated herein by reference describes a multi-threaded processor system.
This earlier patent describes a system with multiple hardware threads which also incorporate co-processor ports. In that system all the threads are homogenous in that they all have the same set of capabilities and the same resources available to them. Various processors build upon the foundation of this system by altering the processor so that it acts like most regular RISC processors but also incorporates features common to DSP processors.
Shown in FIG. 1 is a multi-threaded microprocessor core of the type described in GB2311882. This microprocessor consists of a number of arithmetic pipelines (e.g. data units (5) and address units (4)) along with an instruction scheduler capable of issuing to these pipelines from one of a number of threads where a thread is a separate stream of instructions running on a set of common hardware. Of particular note is the fact that threads do possess some separate resources—most importantly each thread possesses a set of registers all to itself.
In general when making a device with multiple threads it will be the case that the circuit for one thread is designed and then this circuit is replicated for all of the other threads. Circuits of interest include the thread instruction fetch, decode and scheduling materials denoted by (2) on the Figure and the implementation of the registers noted in the address (4) and data units (5).